FPGA Verification Engineer

Our requirements:Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years (Mid-level) or 8+ years (Senior-level) of hands-on experience in FPGA verification and development. Proficiency in VHDL, Verilog, or SystemVerilog for RTL verification. Knowledge of the ASIC design process. Experience with VUnit, cocotb, or UVM. Ability to work independently or strong cooperation skills to work within a cross-functional team. Strong problem-solving and analytical thinking skills. EU citizenship. Candidates must be eligible for employment under a Polish employment contract (UoP). Preferred candidates with:Knowledge in the field of cryptography. Experience with side-channel attacks and countermeasures. Experience with space technologies and requirements. EU/NATO security clearance. Resquant is a rapidly growing deep-tech startup focused on next-generation chip security and quantum-resistant cryptography solutions for dual-use and high-security applications. We develop advanced hardware security technologies designed to address emerging threats in post-quantum computing environments, working at the intersection of cryptography, semiconductor engineering, and secure system architecture. We are building a team of highly skilled engineers passionate about cutting-edge FPGA and ASIC development, secure hardware design, and innovative defense-grade technologies. Position: FPGA Verification Engineer (multiple)Compensation: 22,000–29,000 PLN gross/monthEmployment type: Polish employment contract (Umowa o Pracę / UoP) only; B2B cooperation is not available. Resquant is looking for highly skilled FPGA Verification Engineers for various positions. This is a great opportunity to join a rapidly growing startup at an early stage, working on the latest trends in chip security and cryptography. Main responsibilities:Developing and maintaining verification plans based on design specifications at the block and subsystem level for quantum-resistant cryptographic algorithms and cryptographic processors. Designing and implementing reusable, modular testbenches using VHDL, Verilog, and SystemVerilog. Building simulation environments to verify complex FPGA and digital IPs. Debugging and resolving design and verification issues in collaboration with design engineers. Performing functional and code coverage analysis to ensure verification completeness. Maintaining verification documentation including test plans, coverage reports, test case specifications, and bug tracking logs. Cooperation with ASIC backend team. What do we offer:Full-time Senior and Mid-level positions in a 3-year project. Salary range: 22,000–29,000 PLN gross/month depending on experience and seniority. Employment exclusively under an employment contract (UoP). B2B cooperation is not available. Participation in projects aimed at providing a backbone for chip security for dual-use markets. Flexible working hours. Ability to work remotely (Hybrid/Full). Equity options. Broad technical ownership. Innovation and cutting-edge projects. Career growth and visibility. Opportunity to attend closed events with military representatives. ,[] Requirements: Security, Cryptography, FPGA, VHDL, IPS, Degree, Design process, Backbone Additionally: Career growth, Flexible working hours.