Senior RTL & uArch Designer for SoC (Hybrid)

A global technology consulting firm is looking for an experienced RTL Developer based in Wrocław or other Polish cities. The ideal candidate will have over 7 years of experience in digital design, strong knowledge of Verilog or VHDL, and experience with professional tools like Cadence Genus and Synopsys Design Compiler. This role offers a hybrid working model, access to continuous training, and a commitment to diversity in the workplace. #J-18808-Ljbffr