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  • 850 - 1300 zł / dziennie

     ...Minimum 4 years of experience in VHDL development and synchronous FPGA design Proficiency in synthesis and place & route tools Solid understanding of static timing analysis and timing closure techniques Proven ability to optimize designs for performance and efficiency... 
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    Praca zdalna
    Pełny etat

    Sii Polska

    Lublin
    13 dni temu
  • 850 - 1300 zł / dziennie

     ...in FPGA verification and validation Strong understanding of requirements-based testing methodologies Hands-on experience with VHDL simulation and verification environments Familiarity with coverage analysis and test completeness Experience with hardware testing... 
    Zasugerowane
    Praca zdalna
    Pełny etat

    Sii Polska

    Lublin
    13 dni temu